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MC10H181 4-Bit Arithmetic Logic Unit/ Function Generator
The MC10H181 is a high-speed arithmetic logic unit capable of performing 16 logic operations and 16 arithmetic operations on two four-bit words. Full internal carry is incorporated for ripple through operation. Arithmetic logic operations are selected by applying the appropriate binary word to the select inputs (S0 through S3) as indicated in the tables of arithmetic/logic functions. Group carry propagate (PG) and carry generate (GG) are provided to allow fast operations on very long words using a second order look-ahead. The internal carry is enabled by applying a low level voltage to the mode control input (M). When used with the MC10H179, full-carry look-ahead, as a second order look-ahead block, the MC10H181 provides high-speed arithmetic operations on very long words. This 10H part is a functional/pinout duplication of the standard MECL 10K family part with 100% improvement in propagation delay and no increase in power supply current. * Improved Noise Margin, 150 mV (Over Operating Voltage and Temperature Range) * Voltage Compensated * MECL 10K - Compatible
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24 CDIP-24 L SUFFIX CASE 758 1 24 PDIP-24 P SUFFIX CASE 724 1 1 PLCC-28 FN SUFFIX CASE 776 10H181 AWLYYWW MC10H181P AWLYYWW MC10H181L AWLYYWW
A WL YY WW
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device MC10H181L MC10H181P MC10H181FN Package CDIP-24 PDIP-24 PLCC-28 Shipping 15 Units/Rail 15 Units/Rail 37 Units/Rail
(c) Semiconductor Components Industries, LLC, 2006
June, 2006 - Rev. 8
1
Publication Order Number: MC10H181/D
MC10H181
S3 13 S2 15 S1 17 S0 14 2 F0
LOGIC DIAGRAM
B0 20
A0 21
3 F1
B1 19
A1 18
7 F2
B2 11
A2 16
6 F3
B3 9 8 PG
A3 10 4 GG
5 Cn+4 Cn 22 M 23 VCC1 = Pin 1 VCC2 = Pin 24 VEE = Pin 12
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MC10H181
FUNCTION SELECT TABLE
LOGIC DIAGRAM
13 15 17 14 S0 S1 21 20 18 19 16 11 10 9 22 23 A0 B0 A1 B1 A2 B2 A3 B3 Cn M S2 S3 F0 F1 F2 F3 GG PG Cn+4 Function Select S3 S2 S1 S0 L L L L L 2 3 7 6 4 8 5 L L L H H H H H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H
Logic Functions M is High C = D.C. F F=A F=A+B F=A+B F = Logical "1" F=A*B F=B F=AB F=A+B F=A*B F=AB F=B F=A+B F = Logical "0" F=A*B F=A*B F=A F=A
Arithmetic Operation M is Low Cn is low F F = A plus (A * B) F = A plus (A * B) F = A times 2 F = (A + B) plus 0 F = (A + B) plus (A * B) F = A plus B F = A plus (A + B) F = (A + B) plus 0 F = A minus B minus 1 F = (A + B) plus (A * B) F = A plus (A + B) F = minus 1 (two's complement) F = (A * B) minus 1 F = (A * B) minus 1 F = A minus 1
DIP PIN ASSIGNMENT
VCC1 F0 F1 GG CN + 4 F3 F2 PG B3 A3 B2 VEE 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC2 M CN A0 B0 B1 A1 S1 A2 S2 S0 S3
Pin assignment is for Dual-in-Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).
MAXIMUM RATINGS
Symbol VEE VI Iout TA Tstg Power Supply (VCC = 0) Input Voltage (VCC = 0) Output Current- Continuous - Surge Operating Temperature Range Storage Temperature Range- Plastic - Ceramic Characteristic Rating -8.0 to 0 0 to VEE 50 100 0 to +75 -55 to +150 -55 to +165 Unit Vdc Vdc mA C C C
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MC10H181
ELECTRICAL CHARACTERISTICS (VEE = -5.2 V 5.0%) (See Note 1.)
0 Characteristic Power Supply Current Input Current High Pin 22 Pins 14,23 Pins 13,15,17 Pins 10,16,18,21 Pins 9,11,19,20 Input Current Low Pins 9-11, 13-22 High Output Voltage Low Output Voltage High Input Voltage Low Input Voltage Symbol IE IinH Min - - - - - - 0.5 -1.02 -1.95 -1.17 -1.95 Max 159 720 405 515 475 465 - -0.84 -1.63 -0.84 -1.48 Min - - - - - - 0.5 -0.98 -1.95 -1.13 -1.95 +25 Max 145 450 255 320 300 275 - -0.81 -1.63 -0.81 -1.48 Min - - - - - - 0.3 -0.92 -1.95 -1.07 -1.95 +75 Max 159 450 255 320 300 275 - -0.735 -1.60 -0.735 -1.45 Unit mA A
IinL VOH VOL VIH VIL
A Vdc Vdc Vdc Vdc
1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. AC PARAMETERS
AC Switching Characteristics 0C Characteristic Propagation Delay Rise Time, Fall Time Propagation Delay Rise Time, Fall Time Propagation Delay Rise Time, Fall Time Propagation Delay Rise Time, Fall Time Propagation Delay Rise Time, Fall Time Propagation Delay Rise Time, Fall Time Propagation Delay Rise Time, Fall Time Propagation Delay Rise Time, Fall Time Propagation Delay Rise Time, Fall Time Propagation Delay Rise Time, Fall Time Propagation Delay Rise Time, Fall Time Propagation Delay Rise Time, Fall Time Propagation Delay Rise Time, Fall Time Propagation Delay Rise Time, Fall Time Propagation Delay Rise Time, Fall Time Symbol t+ +, t- - t+, t- t+ +, t+ -, t- +, t- - t+, t- t+ +, t+ -, t- +, t- - t+, t- t+ +, t- - t+, t- t+ +, t- - t+, t- t+ -, t- + t+, t- t+ +, t- + t+, t- t+ +, t- - t+, t- t+ +, t- - t+, t- t+ -, t- + t+, t- t+ +, t+ - t+, t- t+ -, t- + t+, t- t- +, t+ - t+, t- t+ -, t- + t+, t- t+ -, t- + t+, t- Input Cn Cn Cn Cn Cn A1 A1 A1 A1 A1 A1 A1 A1 A1 B1 B1 B1 B1 B1 B1 B1 B1 M M S1 S1 S1 S1 S1 S1 S1 S1 Output Cn+4 Cn+4 F1 F1 F1 F1 F1 F1 PG PG GG GG Cn+4 Cn+4 F1 F PG PG GG GG Cn+4 Cn+4 F1 F1 F1 F1 PG PG Cn+4 Cn+4 GG GG S0,S3 S0,S3 A0,A2,A3,Cn A0,A2,A3,Cn A0,A2,A3,Cn A0,A2,A3,Cn S3,Cn S3,Cn S0,A1 S0,A1 S3,Cn S3,Cn S3,Cn S3,Cn - - A1,B1 A1,B1 A3,B3 A3,B3 A3,B3 A3,B3 A3,B3 A3,B3 Conditions A0,A1,A2,A3 A0,A1,A2,A3 A0 1.0 0.7 1.5 0.7 1.5 0.9 1.5 0.7 1.5 0.5 2.0 0.7 1.5 0.7 1.5 0.7 2.0 0.5 1.5 0.8 1.5 0.7 1.5 0.7 1.5 0.7 1.3 0.5 3.0 2.2 3.7 2.0 3.7 2.4 3.7 2.2 3.6 2.0 4.5 2.3 3.8 2.2 3.7 2.2 4.0 2.0 4.2 2.3 4.5 2.0 4.0 2.0 4.1 2.2 4.5 3.2 1.0 0.7 1.5 0.7 1.5 0.9 1.5 0.7 1.5 0.5 2.0 0.7 1.5 0.7 1.5 0.7 2.0 0.5 1.5 0.8 1.5 0.7 1.5 0.7 1.5 0.7 1.3 0.5 3.0 2.2 3.7 2.0 3.7 2.4 3.7 2.2 3.6 2.0 4.5 2.3 3.8 2.2 3.7 2.2 4.0 2.2 4.2 2.3 4.5 2.0 4.0 2.2 4.1 2.2 4.5 3.2 1.2 0.7 1.6 0.7 1.6 0.9 1.6 0.7 1.6 0.5 2.1 0.7 1.6 0.7 1.6 0.7 2.1 0.5 1.6 0.8 1.6 0.7 1.6 0.7 1.6 0.7 1.4 0.5 3.3 2.4 ns 4.0 2.2 4.0 2.6 3.9 2.4 3.9 2.2 4.8 2.5 4.0 2.4 4.0 2.4 4.3 2.2 4.5 2.5 4.8 2.2 4.3 2.4 4.4 2.4 4.8 3.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min 0.7 0.6 Max 2.0 2.0 +25C Min 0.7 0.6 Max 2.0 2.0 +75C Min 0.7 0.7 Max 2.2 2.2 Unit ns ns ns
Logic high level (+1.11 Vdc) applied to pins listed. All other input pins are left floating or tied to +0.31 Vdc. VCC1 = VCC2 = +2.0 Vdc, VEE = -3.2 Vdc
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MC10H181
PACKAGE DIMENSIONS
PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE D
Y BRK D Z -L- -M- B 0.007 (0.180) U
M
T L-M
M
S
N
S S
-N-
0.007 (0.180)
T L-M
N
S
W
28 1
D
V
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
A Z R E G G1 0.010 (0.250)
S
0.007 (0.180) 0.007 (0.180)
M M
T L-M T L-M
S S
N N
S S
H
0.007 (0.180)
M
T L-M
S
N
S
C
K1 0.004 (0.100) -T- SEATING
PLANE
J
K F VIEW S 0.007 (0.180)
M
VIEW S T L-M
S
T L-M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
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MC10H181
PACKAGE DIMENSIONS
CDIP-24 L SUFFIX CERAMIC DIP PACKAGE CASE 758-02 ISSUE A
B
24 1 13 12
L
P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
-A- N C K G D 24 PL 0.25 (0.010) F
M
J
-T-
SEATING PLANE
DIM A B C D F G J K L N P
INCHES MIN MAX 1.240 1.285 0.285 0.305 0.160 0.200 0.015 0.021 0.045 0.062 0.100 BSC 0.008 0.013 0.100 0.165 0.300 0.310 0.020 0.050 0.360 0.400
MILLIMETERS MIN MAX 31.50 32.64 7.24 7.75 4.07 5.08 0.38 0.53 1.14 1.57 2.54 BSC 0.20 0.33 2.54 4.19 7.62 7.87 0.51 1.27 9.14 10.16
TA
M
-A-
24 1 13 12
PDIP-24 P SUFFIX PLASTIC DIP PACKAGE CASE 724-03 ISSUE D
-B- L C
NOTES: 1. CHAMFERED CONTOUR OPTIONAL. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4. CONTROLLING DIMENSION: INCH. DIM A B C D E F G J K L M N INCHES MIN MAX 1.230 1.265 0.250 0.270 0.145 0.175 0.015 0.020 0.050 BSC 0.040 0.060 0.100 BSC 0.007 0.012 0.110 0.140 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 31.25 32.13 6.35 6.85 3.69 4.44 0.38 0.51 1.27 BSC 1.02 1.52 2.54 BSC 0.18 0.30 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
-T-
SEATING PLANE
K E G F D
24 PL
NOTE 1
N J
24 PL
M 0.25 (0.010)
M
TB
M
0.25 (0.010)
M
TA
M
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC10H181/D

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